Researchers have used Verilator to develop new co-simulation environments, as part of general ASIC and FPGA design flows and in performance and power analysis. The semiconductor industry has been more cautious in its adoption of an open source tool, and has the financial means to use commercial alternatives. Verilator has seen its widest adoption in the academic and open source communities. It is part of the growing body of free EDA software. Verilator is now used within academic research, open source projects and for commercial semiconductor development. The generated models are cycle-accurate and 2-state as a consequence, the models typically offer higher performance than the more widely used event-driven simulators, which can model behavior within the clock cycle.
Verilator is a free and open-source software tool which converts Verilog (a hardware description language) to a cycle-accurate behavioral model in C++ or SystemC. Linux, FreeBSD, Microsoft Windows (via Cygwin )
0 kommentar(er)
